A thin film transistor liquid crystal display (TFT-LCD) is an active matrix type liquid crystal display, which has features such as high contrast, rich colors and high refresh rate.
A display screen is composed of a great amount of pixels that emit light with particular colors, and the colors displayed by each of the pixels can be controlled individually so as to display a picture. Typically, the TFT-LCD has a back light unit. In order to control the color and contrast of each pixel precisely, a thin film field effect transistor with a switch function is required to be disposed at the position of each pixel.
The pixels may have three primary colors, i.e. red (R), green (G) and blue (B), accordingly, red, green and blue filters are disposed corresponding to the position of each pixel. Each of the filters corresponds to one thin film field effect transistor. When the thin film filed effect transistor is turned on, by controlling the on-current magnitude and using the optical activity of liquid crystal molecular filled in each pixel, the optical rotation extent of the liquid crystal molecular is changed, so that the light passing through the filters can be changed and the respective pixels can display distinctive colors.
FIG. 1-2 is a cross-sectional view taken along a cutting line A-A′ in FIG. 1-1. As shown in FIG. 1-2, a thin film filed effect transistor comprises a gate electrode 1, a gate insulating layer 2, an active layer 3, and a source/drain electrode (S/D) layer. The S/D layer comprises a source electrode 4 and a drain electrode 5, and a channel is formed between the source electrode 4 and the drain electrode 5. When a voltage is applied on the gate electrode 1, the source electrode 4 and the drain electrode 5 are communicated through the active layer 3. The active layer 3 comprises a layer of doped amorphous silicon (N+ a-Si) and a layer of amorphous silicon (a-Si). An insulating layer 6 is arranged on the S/D layer. The drain electrode 5 is connected to a pixel electrode 8 through a via hole 7 in the insulating layer 6. The pixel electrode 8 is distributed for each of the pixels in the display region on a glass substrate 9. A common electrode 10 is formed on the glass substrate 9 and under the pixel electrode 8. The common electrode 10 and the pixel electrode 8 constitute an energy storage capacitor.
A method for manufacturing a liquid crystal panel in an existing technology, mainly comprises:
Step S201, forming a first transparent electrode, i.e. a common electrode, on a glass substrate by a mask process.
Since the common electrode on the glass substrate has a certain pattern, the common electrode is shaped by the mask process. The mask process mainly comprises steps of: lamination (application of photoresist), i.e. attaching a layer of photoresist onto the glass substrate; exposure, irradiating or not irradiating the pattern region for the common electrode depending on the property of the photoresist; development, removing the photoresist in the irradiated or un-irradiated region after the exposure so as to form a photoresist pattern; etching, performing an etch process by using the photoresist pattern as a mask, so as to obtain the common electrode pattern.
Step S202, forming a gate electrode on the glass substrate by a mask process.
Similarly, as the gate electrode also has a certain pattern, it needs the mask process to fabricate the gate electrode with the certain pattern.
Step S203, fabricating an S/D layer and an active layer by using a half-tone mask.
A gate insulating layer needs to be formed on the gate electrode before the S/D layer and the active layer are fabricated, in order to protect the gate electrode and make it insulated from the active layer.
The half-tone mask process has the following property: the etching thicknesses in different regions are different during the etching. The un-etched S/D layer and active layer are applied onto the gate insulating layer simultaneously, and the S/D layer and a channel between the source electrode and the drain electrode are formed in one mask process.
Step S204, forming an insulating layer on the S/D layer and forming a via hole in the insulating layer by a mask process.
Step S205, forming a second transparent electrode (pixel electrode) on the insulating layer, and the pixel electrode is connected with the drain electrode through the via hole.
During the aforementioned process of manufacturing liquid crystal panel, since a half-tone mask is employed for the S/D layer and the active layer, etching on the S/D layer and etching on the active layer can be conducted in one mask step. It is desired that an edge of the active layer is aligned with an edge of the S/D layer, as in the form indicated by a dotted line in FIG. 1-2. However, as shown in FIG. 1-3, since the etching methods and the etching rates are different for the S/D metal layer and the active layer, the edge of the active layer is not aligned with the edge of the S/D layer but has a distance of d2 therebetween, and thus the active layer is exposed to the external. In order to avoid the influence of the coupling storage capacitor at the edge of the electrode, a distance d1+d2 and a width of a black matrix (BM) 11 are required to be increased. In such a case, not only the pixel electrical property is influenced, but also the design on the black matrix 11 will be adversely influenced, thereby reducing the aperture ratio.